Technical Field
The invention relates to an analysis and simulation technique for a digital integrated circuit (IC) design, and particularly relates to a timing analysis method for a digital circuit design and a system thereof.
Related Art
In order to simplify design complexity of a digital circuit, a user can use a digital circuit design program and a library model built therein to design the required circuit, and perform circuit function verification on the digital circuit design, so as to determine whether the digital circuit design can successfully satisfy the user's functional requirements. Since implementation of the circuit structure is required to consider a plenty of electronic circuit and electromagnetic properties, for example, consider a layout position of each of the components in the circuit, an influence of a circuit length on signal, timing and power transmission, etc., an auto-place-route (APR) tool is used for subsequent circuit-related implementation and verification.
In order to perform timing analysis for each of the digital circuit designs, timing parameters related to the delay and timing checking are obtained in a gate-level for each of the digital circuit designs according to a circuit structure and variation thereof in a signal simulation method, and these timing parameters may construct a plurality of timing arcs. In this way, the APR tool can analyse a timing model of the circuit design according to the timing arcs without learning a whole circuit structure and component positions. Collection information of the specific timing parameters is referred to as an extracted timing model (ETM). A source of the aforementioned variation may include manufacturing variation, device fatigue, environment variation, phase locked loop (PLL) variation, etc. However, regardless of the type of the variation, the sources of the variation may obviously increase difficulty in analysis and simulation of the digital circuit design, such that these variations have to be accurately counted during the timing analysis.
In the past, a generation flow of the ETM is to produce a different ETM for each operating mode in each circuit design (for example, a single intellectual property (IP) design component), and perform supplement and derating to each of the ETMs according to an on-chip variation thereof, such that each circuit design probably corresponds to a plurality of ETMs. Since the APR tool has to consider whether the timing checking of the circuit design satisfies the user's requirement during a built-in self-test (BIST) phase or a function verification phase, the ETM under each operating mode has to be provided to the APR tool for reference. However, the currently known APR tool cannot read all of the ETMs in a single circuit design, and can only take the firstly-read ETM as a reference of the circuit design, and cannot consider the timing information in the other ETMs. In other words, the current APR tool cannot completely analyze the timing information of all of the ETMs in the single circuit design.
Therefore, how to make the APR tool to successfully perform circuit analysis according to a plurality of the ETMs corresponding to different operating modes of the single circuit design is always a problem in the digital circuit design technique.